The present invention relates to a method for manufacturing a semiconductor device, and is available for, for example, manufacture of a semiconductor device having a nonvolatile memory and a capacitive element.
An EEPROM (Electrically Erasable and Programmable Read Only Memory) has widely been used as an electrically writable and erasable nonvolatile semiconductor memory device. Such a memory device has a conductive floating gate electrode or a trapping insulation film surrounded by an oxide film beneath a gate electrode of a MISFET and holds a charge storage state at the floating gate electrode or the trapping insulation film as memory information and reads out it as a threshold value of a transistor.
The trapping insulation film refers to an insulating film capable of accumulating an electric charge and may include a silicon nitride film or the like as an example. The threshold value of the MISFET is shifted by injection/discharge of the electric charge into/from such a charge storage region to operate the trapping insulation film as a memory element. As the nonvolatile semiconductor memory device using the trapping insulation film, there is known a split gate-type cell using a MONOS (Metal Oxide Nitride Oxide Semiconductor) film.
Further, as a method for forming a gate electrode, there is known a so-called gate last process in which after a dummy gate electrode is formed over a substrate, the dummy gate electrode is replaced with a metal gate electrode or the like. When the gate last process is used, it is difficult to form a capacitive element in which a lower electrode is formed at the same height as the gate electrode and an upper electrode is provided over the lower electrode.
On the other hand, if a capacitive element is used in which a semiconductor substrate is used as a lower electrode and an upper electrode is formed at the same height as a gate electrode, it can be mixedly mounted over the semiconductor substrate together with a memory element or the like formed using the gate last process. In such a capacitive element, a part of the upper electrode is embedded into a trench formed in a main surface of the semiconductor substrate to enable a facing area between the upper electrode and the semiconductor substrate to increase, thereby making it possible to increase the capacity of the capacitive element.
Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2014-154789) has described that a memory cell and a MISFET having a metal gate electrode are formed by using a gate last process.
Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2003-309182) has described that in a capacitive element which generates a capacity between a substrate and an electrode provided over the substrate, a part of the electrode is embedded into a trench defined in an upper surface of the substrate.